1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memory devices and, more particularly, the present invention relates to nonvolatile semiconductor memory devices having multi-level memory cells, and to methods of reading data from nonvolatile semiconductor memory devices.
A claim of priority is made to Korean Patent Application 10-2005-37430, filed on May 4, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
A nonvolatile semiconductor memory device has the capability of retaining stored data even when power is not supplied to the device. Several types of memory cells suitable for use in a nonvolatile semiconductor memory device are well known, one of which is a single transistor-type memory cell as illustrated in FIG. 1.
As shown in FIG. 1, a single transistor-type memory cell MC generally includes a source S and a drain D on a semiconductor wafer, a control gate CG, and a floating gate FG formed between a dielectric oxide DOX and a gate oxide GOX. The floating gate FG traps electrons, and the trapped electrons are used to establish the threshold voltage of memory cell MC. When the nonvolatile semiconductor memory device performs a read operation, the data value stored in memory cell MC is determined by sensing the threshold voltage of memory cell MC.
Typically, in the memory cells MC of a nonvolatile semiconductor memory device, a program operation and an erase operation can be performed repeatedly. In this case, several functions of the single transistor-type memory cells MC are determined by various voltages applied thereto. Each single transistor-type memory cell MC is programmed by causing electrons to move to the floating gate FG. The electrons moving to the floating gate FG are generated by Fowler-Nordheim tunneling (FN), electron injection, etc. Electron injection is performed by channel hot-electron injection (CHE), channel-initiated secondary electron injection (CISEI), etc. Further, Fowler-Nordheim tunneling (FN) is generally used in flash memory devices for erasing data all at once.
A single transistor-type memory cell, such as memory cell MC, typically stores one of two possible threshold voltage levels. A memory cell that stores one of two possible threshold voltage levels will be referred to herein as a 2-level memory cell. As shown in FIG. 2, a data value in a 2-level memory cell is represented by a threshold voltage set to one of two levels. For example, if the threshold voltage of memory cell MC is lower than a reference voltage VR, its data value is read as “1”, and if the threshold voltage of memory cell MC is higher than reference voltage VR, its data value is read as “0”.
In order to increase the integration degree of memory device, a 4-level memory cell has been developed. As shown in FIG. 3, a 4-level memory cell can be programmed to one of four threshold voltage groups. Consequently, the 4-level memory cell can store data having any one of four values. Therefore, a nonvolatile semiconductor memory device having 4-level memory cells (hereinafter referred to as a “multi-level nonvolatile semiconductor memory device”) has a data storage capacity that is about two times the storage capacity of a nonvolatile semiconductor memory device having 2-level memory cells.
Generally, in the memory cells of a conventional multi-level nonvolatile semiconductor memory device, each threshold voltage group corresponds to one of the two-bit data values “11,” “10,” “01,” and “00.” As shown in FIG. 2, the threshold voltage group corresponding to “11” has the lowest threshold voltage among the threshold voltage groups, the threshold voltage group corresponding to “10” has a greater threshold voltage than the threshold voltage group corresponding to “11,” the threshold voltage group corresponding to “01” has a greater threshold voltage than the threshold voltage group corresponding to “10,” and the threshold voltage group corresponding to “00” has a greater threshold voltage than the voltage group corresponding to “01.” The threshold voltage groups can be identified using first, second, and third reference voltages VR1, VR2, and VR3, respectively, wherein first reference voltage VR1 is less than second reference voltage VR2, and second reference voltage VR2 is less than third reference voltage VR3. When reading the LSB (least significant bit) of a data value, a bit line sensing process includes applying each of the first through third reference voltages VR1 through VR3 to the gate terminal of a selected memory cell and mapping the threshold voltage of the selected memory cell to a bit line.
The conventional multi-level nonvolatile semiconductor memory device includes a sequence of operations which precharge each bit line to a predetermined precharge voltage before the bit line sensing process is executed. This sequence of precharge operations of the conventional multi-level nonvolatile memory device is disadvantageous in that it takes a relatively long time to execute.